FIG. 1 depicts a portion of a dynamic random access memory (DRAM) device 1 which stores digital information or data in an arrangement of memory cells 3. An arrangement of memory cells is known as an array. The cells 3 are arranged in the array in a configuration of intersecting rowlines 5 and column lines 6. The rowlines 5 may also be referred to as wordlines. Each memory cell 3 comprises a storage capacitor 7 capable of holding a charge and a metal-oxide semiconductor field effect transistor (MOSFET) for accessing the capacitor charge; hereinafter this transistor is referred to an as access transistor 8.
The charge is a voltage potential referred to as a data bit and is typified as having either a high voltage "1" or a low voltage "0". Therefore, the memory has two states, often thought of as the true logic state and the complementary logic state. The data bit is amplified and latched to the digit 9 and digit bar 10 lines by the N-sense amplifier 11. The digit line 9 and the digit bar line 10 form a digit line pair. The P-sense amplifier pulls one digit line of the digit line pair to a high potential, usually the supply potential, V.sub.cc, while the N-sense amplifier pulls the remaining digit line to a ground potential.
There are two normal operations available in a DRAM memory, a bit of data may be stored in a specified cell in the write mode or a bit of data may be retrieved from a specified cell in the read mode. The data is either transferred from the digit line pair in electrical communication with the specified cell to Input/Output (I/O) lines 12 in the read mode or transferred from the I/O lines 12 to the digit line pair in the write mode. In either case, the data is transferred through MOSFETs used as switching devices and called decode transistors 13. For each bit of data stored, its true logic state is available at a first I/O line and it complementary logic state is available at a second I/O line, designated I/O*. For purposes of this discussion, I/O and I/O* are often referred to as just I/O lines 12. Each cell 3 is electrically referenced to one digit line 9 and the corresponding digit bar line 10 through the N-sense amplifiers 11.
In order to read from or write to a cell 3, the particular cell 3 in question must be selected or addressed. A particular cell 3 is selected when a row decoder (not shown) activates a rowline 5 and a column decoder (not shown) activates a column line 6. The electrical intersection of the activated rowline 5 and the activated column line 6 determines which cell 3 as has been selected.
For example, during a read mode when a cell 3 has been selected the access transistor 8 of the selected cell 3 actuates and couples the charge stored on the storage capacitor 7 of the cell 3 to its respective digit line. The charge stored in the storage capacitor 7 has a potential different than the potential of the digit line. This difference between the potential of the storage capacitor 7 and the potential of the digit line is the cell margin. The N-sense amplifier senses the cell margin and determines what data has been stored in the cell. Next the N-sense amplifier amplifies the potential of the digit line to reflect the value of the potential stored in the cell. Once amplified the digit line in electrical communication with the selected cell has a potential representing the data bit stored in the storage capacitor, and the remaining digit line of the digit line pair has a potential equal to the complement of the data bit stored in the storage capacitor of the selected cell.
Typically the DRAM is connected electrically between a supply potential, V.sub.cc, and a ground reference potential. The supply potential has often been equal to 5 volts but in more recent circuit generations it is less than 5 volts, typically 3.3 volts. Between cycles of cell selection it is necessary to equilibrate the digit lines of each digit line pair to the same voltage, often V.sub.cc /2 or 3/5 V.sub.cc. This equilibration of the digit lines occurs during what is often referred to as the precharge cycle. An equilibrate transistor 15 in parallel with the N-sense amplifier 11 essentially shorts digit 9 and digit bar 10 together and holds them at the equilibrate potential during precharge. This equilibration is necessary so that the digit lines are ready to receive data.
During normal operation one set of the isolation (ISO) gates, either 17 or 18, is deactuated to isolate the digit line capacitance to the side of the N-sense amplifier in which the selected cell 3 is located. This deactuation of one set of the isolation gates reduces the stray capacitance of the digit 9 and digit bar 10 by half thereby increasing the signal to noise (S/N) ratio. The S/N is equal to the storage cell capacitance divided by the digit line capacitance. Increasing the S/N ratio increases the cell margin and makes the part more reliable. As the cell margin increases the N-sense amplifier senses the data with greater accuracy. A part becomes more reliable with a sense amplifier's ability to sense and latch data correctly with decreasing cell margins.
There exists a need to reduce test time thereby reducing costs associated with testing large memory devices. There also exists a need for a monolithic memory device having a test mode circuit and a method which screens out sub-standard devices that usually need long and complicated test patterns. Screening out sub-standard devices reduces test times and costs.